1. Field of the Invention
The present invention relates to a semiconductor device, more particularly, to a semiconductor device with a drift layer having a so-called floating structure.
2. Description of the Related Art
In recent years, demands for a power MOSFET has greatly increased not only in a market for large-current/high-breakdown voltage switching power supplies (for example, a breakdown voltage of 600V) but also in a market for energy-saving switching devices for mobile communication devices (for example, a breakdown voltage of 30V) such as note-type personal-computers.
The power MOS transistor in such an energy-saving switching market is required to reduce the capacitance between a gate and a drain. Reducing the gate-drain capacitance allows a low voltage operation, which makes it possible to be directly driven by a battery voltage. It also allows a low ON-state resistance, and a switching loss reduction.
On the other hand, although the ON-state resistance of a MOS transistor mainly consists of a channel resistance and a drift resistance. A so-called super-junction structure and a so-called floating structure are known as a structure of a MOS transistor for reducing a drift resistance.
The super-junction structure forms a drift layer by embedding a longitudinal strip-like p type pillar layers and n type pillar layers in turn in a transverse direction (for example, See JP 2003-273355A). A super-junction structure may spread a depletion layer in a transverse direction along the direction the p/n pillar layers are arranged when a MOS transistor is non-conductive. This makes the breakdown voltage of the element higher. In addition, a pseudo non-doped layer may be generated when the charge quantities (impurity quantities) included in the p type pillar layers and the n type pillar layers are made equal. This is effective to retain a high breakdown voltage and cause a current flowing through highly doped, n−type pillar layers, thereby realizing a low on-resistance that exceeds the material limit.
A floating structure is formed by burying a p type buried layer as a floating layer in an n type epitaxial layer as a drift layer by ion implantation, for example. The p type buried layer is not electrically connected to a p type base layer where a MOS transistor is formed. Also in this floating structure, the depletion layer formed between the p type buried layer and the n type epitaxial layer when a MOS transistor is non-conductive enables the breakdown voltage to be maintained at a high value. This floating structure is effective for improvement in properties of MOS transistors with a breakdown voltage of about 60V to 100V. Especially, when compared to a MOS transistor with the super-junction structure where a p type pillar is formed in the same depth, it has been confirmed that the MOS transistor with a floating structure has an improved trade-off between an ON-state resistance and a breakdown voltage.
However, the MOS transistor with such a floating structure has a long turn-on time as a problem. Specifically, once the p type buried layer in the MOS transistor is depleted at the OFF state, the transistor does not moves to a normal ON state until the depletion layer in the p type buried layer disappears.
Moreover, the depletion layer extends to the peripheral area of the p type buried layer just after the turn-on. This causes the carrier-conduction area to be narrowed, the resistance of the element to become high, and the switching loss to become larger.